Today begins week 2 of building out the Raizing Core which will support Batrider, Garegga and Battle Bakraid. In week 1 I focused mainly on learning verilog, and also as an exercise, building out most of the ymz280b audio module. This exercise enabled me to adapt to the design mechanics of hardware design as it is very different than designing software, which I am used to. In addition to that, I also prepared an inventory of module component availability to see what new modules I might need to create in order to support all 3 games. Thus far, I found most things are in fact available, with the exception of the GP9001 graphics decoder chip and the ymz280b sound module.
Now, I will focus my efforts on getting to the point of “first signs of life” from the core. In my case, that means:
- Mapping out the ROM and RAM regions
- Preparing the MRA file to load the ROM.
- Creating a loader to load the ROM into MiSTer’s SDRAM.
- Porting some or all of the GP9001 graphics decoding and pixel/ sprite display code from MAME and designing what that module might look like.
- BONUS: Mapping controls and dip switch values.
So, my goal for the week is to get items 1-3, and start on #4. I have already done item #2 last night, and researched into #3. #1 is readily available from MAME and other sites, but I have the real Garegga board if I have to take a look and trace something if necessary. However, I am expecting MAME and/or FBA sources have the information I need to hook up everything generally. Then, I will look to the real board for measuring timing values and adjusting where needed in the clocks later on.